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2M x 8 Bits x 4 Banks Synchronous DRAM
FEATURES

WED48S8030E
DESCRIPTION
The WED48S8030E is 67,108,864 bits of synchronous high data rate DRAM organized as 4 x 2,097,152 words x 8 bits. Synchronous design allows precise cycle control with the use of system clock, I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Available in a 54 pin TSOP type II package the WED48S8030E is tested over the industrial temp range (40C to +85C) providing a solution for rugged main memory applications.
Single 3.3V power supply Fully Synchronous to positive Clock Edge Clock Frequency = 125, 100MHz SDRAM CAS# Latency = 2 Burst Operation *Sequential or Interleave *Burst length = programmable 1,2,4,8 or full page *Burst Read and Write *Multiple Burst Read and Single Write
DATA Mask Control
Auto Refresh (CBR) and Self Refresh *4096 refresh cycles across 64ms Automatic and Controlled Precharge Commands Suspend Mode and Power Down Mode Industrial Temperature Range

FIG. 1
Pin Configuration
VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE# CAS# RAS# CE# BA0 BA1 A10/AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC/RFU DQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
Pin Description
A0-11 BA0, BA1 CE# WE# CK CKE DQ0-7 DQM RAS# CAS# VCC VCCQ VSS VSSQ NC Address Inputs Bank Select Addresses Chip Select Write Enable Clock Input Clock Enable Data Input/Output Data Input/Output Mask Row Address Strobe Column Address Strobe Power (3.3V) Data Output Power Ground Data Output Ground No Connection
TERMINAL CONNECTIONS
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
(TOP VIEW)
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INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CK CKE CE# RAS#, CAS# WE# BA0,BA1 Type Input Input Input Input Input Input Signal Pulse Level Pulse Pulse Level Level Polarity Positive Edge Active High Active Low Active Low -- --
WED48S8030E
A0-11, A10/AP
DQ0-15 DQM VCC, VSS VCCQ, VSSQ
Input/ Output Input
Level Pulse
-- Mask Active High
Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CE# disable or enable device operation by masking or enabling all inputs except CK, CKE and DQM. When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the operation to be executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge. Data Input/Output are multiplexed on the same pins The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Power and ground for the input buffers and the core logic. Isolated power and ground for the output buffers to improve noise immunity.
Supply Supply
Absolute Maximum Ratings
Parameter Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Symbol VCC VIN VOUT TOPR TSTG PD IOS Min -1.0 -1.0 -1.0 -40 -55 -- -- Max +4.6 +4.6 +4.6 +85 +125 1.0 50 Units V V V C C W mA
Recommended DC Operating Conditions
(Voltage Referenced to: VSS = 0V, TA = 40C to +85C)
Symbol VCC VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -- -10 -10 Typ 3.3 3.0 -- -- -- -- -- Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage (IOH = -2mA) Output Low Voltage (IOL = 2mA) Input Leakage Voltage Output Leakage Voltage Max 3.6 VCC +0.3 0.8 -- 0.4 10 10 Unit V V V V V A A
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(TA = 25C, f = 1MHz, VCC = 3.3V to 3.6V) Parameter Input Capacitance
Input Capacitance (CK, CKE, RAS#, CAS#, WE#, CE#, DQM)
Capacitance
Symbol CI1 C12 COUT
Max 4 4 5
Unit pF pF pF
Input/Output Capacitance (DQ)
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OPERATING CURRENT Characteristics
(VCC = 3.3V, TA = 40C to +85C)
Symbol ICC1 ICC4 ICC2P ICC2PS ICC1N ICC1NS ICC3P ICC3PS ICC3N ICC3NS ICC5 ICC6 Parameter Operating Current (One Bank Active) (1) Operating Current (Burst Mode) (1) Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode Precharge Standby Current in Power Down Mode Active Standby Current in Non-Power Down Mode (One Bank Active) Refresh Current (2) Self Refresh Current
NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms.
WED48S8030E
Conditions Burst Length = 1, tRC tRC(min) Page Burst, 2 banks active, tCCD = 2 clocks CKE VIL(max), tCC = 15ns CKE, CK VIL(max), tCC = , Inputs Stable CKE = VIH, tCC = 15ns, Input Change every 30ns CKE VIH(min), tCC = , No Input Change CKE VIL(max), tCC = 15ns CKE VIL(max), tCC = CKE = VIH, tCC = 15ns, Input Change every 30ns CKE VIH(min), tCC = , No Input Change tRC tRC(min) CKE 0.2V
-8 100 160 2 2 20 10 5 5 20 10 190 2
-10 95 130 2 2 20 10 5 5 20 10 175 2
Units mA mA mA mA mA mA mA mA mA mA mA mA
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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AC CHARACTERISTICS
Parameter Clock Cycle Time (1) CAS Latency = 3 CAS Latency = 2
WED48S8030E
OPERATING AC PARAMETERS
(Vcc = 3.3V, TA = -40C to +85C) Symbol tCC tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD Min 7.5 10 3 2.5 2.5 1.5 0.8 1 5.4 15 20 20 45 65 65 1 1 1 1 2 1 20 20 20 50 70 70 1 1 1 1 2 1 -8 Max 1000 1000 5.4 Min 10 10 3 3.5 3 2 1 1 6 -10 Max 1000 1000 6 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CK CK CK CK ea
Clock to valid Output delay (1,2) Output Data Hold Time (2) Clock HIGH Pulse Width (3) Clock LOW Pulse Width (3) Input Setup Time (3) Input Hold Time (3) CK to Output Low-Z (2) CK to Output High-Z Row Active to Row Active Delay (4) RAS# to CAS# Delay (4) Row Precharge Time (4) Row Active Time (4) Row Cycle Time - Operation (4) Row Cycle Time - Auto Refresh (4,8) Last Data in to New Column Address Delay (5) Last Data in to Row Precharge (5) Last Data in to Burst Stop (5) Column Address to Column Address Delay (6) CAS Latency = 3 Number of Valid Output Data (7) CAS Latency = 2
100,000
100,000
NOTES: 1. Parameters depend on programmed CAS# latency. 2. If clock rise time is longer than 1ns, (tRISE/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If tRISE & tfall are longer than 1ns, [(tRISE + tFALL)/2]-1ns should be added to the parameter. 4. The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self refresh exit.
REFRESH CYCLE PARAMETERS
Parameter Refresh Period Self Refresh Exit Time Symbol tREF tSREX Min -- tRFC -8 Max 64 -- Min -- tRFC -10 Max 64 -- Units ms ns Notes 1, 2 3
NOTES: 1. 4096 cycles. 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 3. The self refresh is exited by restarting the external clock and then asserting CKE high. This must be followed by NOPs for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation.
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COMMAND TRUTH TABLE
Function CKE Previous Cycle H H H H H H H H H H H H H L H H X X Current Cycle X H L X X X X X X X X X X X X X L H CE# RAS# CAS# WE# DQM BA
WED48S8030E
A10/AP A9-0
A12, A11,
Notes
Register Refresh Precharge
Mode Register Set Auto (CBR) Entry Self Refresh Single Bank Precharge Precharge all Banks
Bank Activate Write Auto Precharge Disable Auto Precharge Enable Read Auto Precharge Disable Auto Precharge Enable Burst Termination No Operation Device Deselect Clock Suspend/Standby Mode Data Write/Output Enable Mask/Output Disable Power Down Entry Mode Exit
L L L L L L L L L L L L H X X X H H
L L L L L L H H H H H H X X X X X X
L L L H H H L L L L H H X X X X X X
L H H L L H L L L H L H X X X X X X
X X X X X X X X X X X X X X L H X X
X X BA X BA BA BA BA BA X X X X X X X X
OP CODE X X X X L X H X Row Address L Column Address H L H X X X X X X X X Column Address X X X X X X X X
2 2 2 2 2 2 3
4 5 5 6 6
(X = Don't Care, H = Logic High, L = Logic Low) NOTES: 1. All of the SDRAM operations are defined by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock. 2. Bank Select (BA), if BA = 0 then bank A is selected, if BA = 1 then bank B is selected. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS# latency. 4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations, therefore the device can't remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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CLOCK ENABLE (CKE0) TRUTH TABLE
CKE Current State Previous Cycle H L L L L L L H L L H H H H H H H H H H H L H Any State other than listed above H L L Current Cycle X H H H H H L X H H X H H H H H L L L L H X H L H L CE# X H L L L L X X H L L H L L L L H L L L L X X X X X RAS# X X H H H L X X X X H X H L L L X H L L L X X X X X Command CAS# X X H H L X X X X X L X X H L L X X H L L X X X X X WE# X X H L X X X X X X L X X X H L X X X H L X X X X X BA0-1 X X X X X X X X X X X A0-11 X X X X X X X X X X
WED48S8030E
Action INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down Mode exit, all banks idle ILLEGAL Maintain Power Down Mode Refer to the Idle State section of the Current State Truth Table
Notes 1 2 2 2 2 2 1 2 2 2 3
Self Refresh
Power Down
X X OP Code
CBR Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table
4 3 4 4
All Banks Idle
X X OP Code X X X X X X X X X X
Entry Self Refresh Mode Register Set Power Down Refer to the Operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
5
NOTES: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satisfied before any command other than Exit is issued. 3. The address inputs (A11-0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table.
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MODE REGISTER SET TABLE
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
WED48S8030E
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency BT
Burst Length
*Should program M11, M10 = "0, 0" to ensure compatability with future devices.
Burst Length M2 M1 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 M0 0 1 0 1 0 1 0 1 M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved
M3 0 1
Burst Type Sequential Interleaved
M6 M5 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1
M4 0 1 0 1 0 1 0 1
CAS Latency RRserved Reserved 2 3 Reserved Reserved Reserved Reserved
M8 0
M7 0
M6-M0 Defined
Operating Mode Standard Operation All other states reserved
M9 0 1
Write Burst Mode Programmed Burst Length Single Location Access
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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CURRENT STATE TRUTH TABLE
Current State Command CE# L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H RAS# L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X CAS# L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X WE# L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X BA0-1 X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X
8
WED48S8030E
Idle
Row Active
Read
Write
Read with Auto Precharge
Description Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Start Read Start Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
Action Set the Mode Register Start Auto orSelf Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Write; Determine if Auto Precharge Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst
Notes 2 2,3
4 2 2 5
6 2 7,8 7,8
4 8,9 8,9
4 8,9 8,9
4 4
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CURRENT STATE TRUTH TABLE (cont.)
Current State Command CE#
L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H
WED48S8030E
RAS#
L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X
CAS#
L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X
WE#
L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X
BA0-1
X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X
A11, A10/AP-A0
OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X
9
Description
Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
Action
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD No Operation; Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL No Operation; Row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL
Notes
Write with Auto Precharge
4 4
Precharging
4 4 4
Row Activating
4 4,10 4 4
Write Recovering
4 4 9 9
Write Recovering with Auto Precharge
4 4 4,9 4,9
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CURRENT STATE TRUTH TABLE (cont.)
Current State Command CE#
L L L L L L L L H L L L L L L L L H
WED48S8030E
RAS#
L L L L H H H H X L L L L H H H H X
CAS#
L L H H L L H H X L L H H L L H H X
WE#
L H L H L H L H X L H L H L H L H X
BA0-1
X X BA BA BA X X X X X BA BA BA X X X
A11, A10/AP-A0
OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X
Description
Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
Action
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles
Notes
Refreshing
Mode Register Accessing
NOTES: 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. Both Banks must be idle otherwise it is an illegal action. 3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered. 4. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS#) must be satisfied. 7. The RAS# to CAS# Delay (tRCD) must occur before the command is given. 8. Address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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WED48S8030E
FIG. 2 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS# LATENCY=3, BURST LENGTH=1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
tCC
CKE
tCH
tCL
HIGH
tRCD tRAS
CE#
tRCD
tSS
tSH
tRP
tSS
RAS#
tSH
tSS
CAS#
tSH
tCCD
tSS
ADDR
Ra
tSH
Ca
tSS
Cb
tSH
Cc Rb
Note 2
Note 2, 3
Note 2, 3
Note 2, 3 Note 4
Note 2
BA
BS
BS
BS
BS
BS
BS
A10/AP
Ra
Note 3
Note 3
Note 3
Note 4
Rb
tRAC tSAC
DQ
Qa
tSS
Db
tSH
Qc
tSLZ
WE#
tOH
tSS
tSH
tSS
DQM
tSH
Row Active
Read
Write
Read Precharge
Row Active
DON'T CARE
NOTES: 1. All input except CKE & DQM can be don't care when CE# is high at the CK high going edge. 2. Bank active & read/write are controlled by BA0~BA1.
BA0 0 0 1 1
BA1 0 1 0 1 BA0 0 0 1 1 x
Active & Read/Write Bank A Bank B Bank C Bank D BA1 0 1 0 1 x Precharge Bank A Bank B Bank C Bank D All Banks
3.
Enable and disable auto precharge function are controlled by A10/AP in read/ write command.
A10/AP 0
BA0 0 0 1 1 0 0 1 1
BA1 0 1 0 1 0 1 0 1
Operation Distribute auto precharge, leave bank A active at end of burst Disable auto precharge, leave bank B active at end of burst Disable auto precharge, leave bank C active at end of burst Disable auto precharge, leave bank D active at end of burst Enable auto precharge, precharge bank A at end of burst Enable auto precharge, precharge bank B at end of burst Enable auto precharge, precharge bank C at end of burst Enable auto precharge, precharge bank D at end of burst
4.
A10/AP and BA0-BA1 control bank precharge when precharge command is asserted.
A10/AP 0 0 0 0 1
1
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FIG. 3
0
WED48S8030E
POWER UP SEQUENCE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
High level is necessary
CE#
tRP
RAS#
tRFC
tRFC
CAS#
ADDR
Key
RAa
BA
A10/AP
RAa
DQ
HIGH-Z
WE#
DQM
High level is necessary
Precharge (All Banks)
Auto Refresh
Auto Refresh
Mode Register Set Row Active (A-Bank)
DON'T CARE
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WED48S8030E
FIG. 4 READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
Note 1
HIGH
tRC
CE#
tRCD
RAS#
Note 2
CAS#
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
Rb
Note 3
tRAC
tSHZ tSAC
Qa0
Note 4
tOH
Qa1 Qa2 Qa3 Db0 Db1 Db2
tRDL
Db3
CL = 2 DQ
CL = 3
tRAC
Note 3
tSAC
Qa0
tOH
Qa1 Qa2
tSHZ
Qa3
Note 4
tRDL
Db0 Db1 Db2 Db3
WE#
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS# Latency - 1) number of valid output data is available after Row precharge. Last valid output will be HiZ(tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS# latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst).
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 13 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED48S8030E
FIG. 5 PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE#
tRCD
RAS#
Note 2
CAS#
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A10/AP
Ra
tRDL
CL = 2 DQ CL = 3
Qa0 Qa1 Qb0 Qb1 Dc0 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1
tCDL
Dc1 Dd0 Dd1
WE#
Note 1
Note 3
DQM
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 14 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED48S8030E
FIG. 6 PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
Note 1
HIGH
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
BA
A10/AP
RAa
RBb
CL = 2 DQ
CL = 3
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2 QBb3
QAc0
QAc1
QBd0
QBd1 QAe0
QAe1
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0 QBd1
QAe0
QAe1
WE#
DQM
Row Active (A-Bank)
Row Active (B-Bank) Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. CE# can be don't cared when RAS#, CAS# and WE# are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 15 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED48S8030E
FIG. 7 PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
BA
A10/AP
RAa
RBb
tCDL
DQ
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
tRDL
DBd1
WE#
Note 1
DQM
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank)
Write (B-Bank)
Write (A-Bank)
Write (B-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 16 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED48S8030E
FIG. 8 READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE#
RAS#
CAS#
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
A10/AP
RAa
RBb
RAc
tCDL
CL = 2
DQ CL = 3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3
Note 1
QAc0
QAc1
QAc2
QAc0
QAc1
WE#
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Row Active (B-Bank)
Write (B-Bank) Row Active (A-Bank)
Read (A-Bank)
DON'T CARE
NOTE: 1. tCDL should be met to complete write.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 17 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED48S8030E
FIG. 9 READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE#
RAS#
CAS#
ADDR
Ra
Rb
Ca
Cb
BA
A10/AP
Ra
Rb
CL = 2 DQ CL = 3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
WE#
DQM
Row Active (A-Bank)
Read with Auto Precharge (A-Bank) Row Active (B-Bank)
Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
DON'T CARE
NOTE: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (in the case of Burst Length=1 & 2 and BRSW mode)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 18 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED48S8030E
FIG. 10 CLOCK SUSPENSION & DQM OPERATION CYCLE @ CAS# LATENCY=2, BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CE#
RAS#
CAS#
ADDR
Ra
Ca
Cb
Cc
BA
A10/AP
Ra
tSHZ
DQ
Qa0 Qa1 Qa2 Qa3 Qb1
tSHZ
Qb1 Dc0 Dc2
WE#
Note 1
DQM
Row Active
Read
Clock Suspension
Read
Read DQM Write
Write DQM Clock Suspension
Write DQM
DON'T CARE
NOTE: 1. DQM is needed to prevent bus contention.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 19 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED48S8030E
FIG. 11 READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH=FULL PAGE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
Note 2
1
1
CL = 2 DQ
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
2
2
CL = 3
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
WE#
DQM
Row Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is same as the case of RAS# interrupt. Both cases are illustrated in above timing diagram. See the label 1, 2. But at burst write, Burst stop and RAS# interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle." 3. Burst stop is valid at every burst length.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 20 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED48S8030E
FIG. 12 WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @ BURST LENGTH=FULL PAGE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
tBDL
tRDL
Note 2
DQ
DAa0
DAa1
DAa2
DAa3
DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
WE#
DQM
Row Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 21 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED48S8030E
FIG. 13 BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
Note 1
CKE
HIGH
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
A10/AP
RAa
RBb
RAc
CL = 2 DQ CL = 3
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
WE#
DQM
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank) Read with Auto Precharge (A-Bank)
Row Active (A-Bank) Write with Auto Precharge (B-Bank)
Read (A-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. BRSW mode is enabled by setting As "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 22 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED48S8030E
FIG. 14 ACTIVE/PRECHARGE POWER DOWN MODE @ CAS# LATENCY=2, BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
Note 2
tSS
CKE
Note 1 Note 3
tSS
tSS
CE#
RAS#
CAS#
ADDR
Ra
Ca
BA
A10/AP
Ra
tSHZ
DQ
Qa0 Qa1 Qa2
WE#
DQM
Precharge Power-Down Entry
Row Active Active Precharge Power-Down Power-Down Exit Entry
Read Active Power-Down Exit
Precharge
DON'T CARE
NOTES: 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1 CK + tSS prior to Row active command. 3. Cannot violate minimum refresh specification (64ms).
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 23 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 15 SELF REFRESH ENTRY & EXIT CYCLE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED48S8030E
17
18
19
CLOCK
tSS
CKE
Note 1
Note 2 Note 3 Note 4
tRFC min
Note 6
CE#
Note 5
RAS#
Note 7
CAS#
ADDR
BA
A10/AP
DQ
HI-Z
HI-Z
WE#
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
DON'T CARE
NOTES: TO ENTER SELF REFRESH MODE 1. CE#, RAS# & CAS# with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low." Once the device enters self refresh mode, minimum tRAS# is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CE# starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 24 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 16 MODE REGISTER SET CYCLE
0 1 2 3 4 5 6
WED48S8030E
FIG. 17 AUTO REFRESH CYCLE
0 1 2 3 4 5 6 7 8 9 10
CLOCK
CKE
HIGH
HIGH
CE#
Note 2
tRFC
RAS#
Note 1
CAS#
Note 3
ADDR
Key
Ra
DQ
HI-Z
HI-Z
WE#
DQM
MRS
New Command
Auto Refresh
New Command
DON'T CARE
NOTES: Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE 1. CE#, RAS#, CAS#, & WE# activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS# activation. 3. Please refer to Mode Register Set table.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 25 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PACKAGE DIMENSION:54 PIN TSOP II
22.35 (0.880) 22.10 (0.870) Note 1 VIEW A
WED48S8030E
10.27 (0.405) 10.03 (0.395) Note 2
11.96 (0.471) 11.56 (0.455) 0.15 (0.006) 0.05 (0.002) 0.80 (0.0315) TYP 0.51 (0.020) 0.25 (0.010)
1.20 (0.047) MAX 0.61 (0.024) 0.41 (0.016)
SEE VIEW A
0-8
0.203 (0.008) 0.125 (0.005)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: 1. Dimension does not include 0.006 inch Flash each side. 2. Dimension does not include 0.010 inch Flash each side.
ORDERING INFORMATION
Part Number WED48S8030E8SI WED48S8030E10SI Organization 2Mx8bitsx4banks 2Mx8bitsx4banks Operating Frequency 125MHz 100MHz Package 54 TSOP II 54 TSOP II
NOTE: This product does not include the prefix "WED" for part marking due to package size constraints.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. February, 2002 Rev. 2 26 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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